IEICE Electronics Express
Online ISSN : 1349-2543
A Bypass-Based Low Latency Network-on-Chip Router
Peng GuoQingbin LiuRuizhi ChenLei YangDonglin Wang
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JOURNALS FREE ACCESS Advance online publication

Article ID: 16.20181147

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Abstract

As the most critical components of Network on chip (NoC), the routers need to select suitable output ports and guarantee every flit accesses the hardware resource exclusively. Thus they are normally designed with several pipelines. However, most flits don't compete for the same output port with other flits in real applications. In this work, we introduce a bypass path to the traditional router thus the non-conflict flits can be forwarded directly. Combined with several other optimizations, we propose a bypass-based low latency NoC router (BNR). When no congestion occurs, BNR can transfer the flit through the bypass path with only one cycle. Otherwise, the flits are transferred through the conventional path with two hops. Besides, we also present a simplified version, BNR-S. Compared with BNR, it only bypasses the short packets and will reduce the area overhead significantly. For the synthetic traffic with different injection rate, BNR achieves 1.48x and 1.31x speedup than the two baselines while BNR-S achieves 1.3x and 1.15x. They also bring obvious benefits for several real applications. In addition, the experiments also illustrate that the proposed bypass mechanism can reduce dynamic power.

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