A 1GS/s 12-bit Pipelined Folding ADC with a novel encoding algorithm

Huasen Liu; Danyu Wu; Lei Zhou; Jian Luan; Xuan Guo; Dong Wang; Jin Wu; Xinyu Liu

doi:10.1587/elex.16.20181150

This article has now been updated. Please use the final version.

A 1GS/s 12-bit Pipelined Folding ADC with a novel encoding algorithm

Huasen Liu, Danyu Wu, Lei Zhou, Jian Luan, Xuan Guo, Dong Wang, Jin Wu, Xinyu Liu

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Keywords: Analog-to-digital converter, folding and interpolating, odd folding factor, encoding algorithm

JOURNAL FREE ACCESS Advance online publication

Article ID: 16.20181150

DOI https://doi.org/10.1587/elex.16.20181150

The final version of this article is now available: Vol. 16 (2019), No. 7 pp. 20181150-20181150

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Abstract

In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40nm CMOS technology is presented. A new encoding algorithm based on distributed quantization is proposed to simplify the quantization process of the structure with odd folding factor and reduce the hardware consumption of the circuit. The ADC achieves spurious free dynamic range (SFDR) > 72dB and signal-to-noise and distortion ratio (SNDR) > 57dB in low input frequencies.

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