A 140 GHz Area-and-Power-Efficient VCO using Frequency Doubler in 65 nm CMOS

抄録

This paper presents a compact, low-phase-noise and low-power D-band VCO with the tuning range from 140.1 to 143.5 GHz. To improve the area and power efficiency, we avoid using signal amplification and matching circuits in the VCO, where a 70 GHz LC oscillator is directly coupled to a frequency doubler. The layout of the transistors is optimized so that the signal loss and reflection are minimized. The proposed VCO fabricated in a 65 nm CMOS technology occupies the core area of 0.05 mm². It achieves the output power of −8 dBm and the phase noise of −108.2 dBc/Hz at 10 MHz offset with the power consumption of 24 mW from 1 V supply, which leads to the figure-of-merit (FoM) of −177.4 dBc/Hz.