Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits

Abstract

A flexible and multipurpose Single Event Effects (SEEs) testing system was developed for evaluating the reliability of nanoscale Very Large Scale Integrated Circuit (VLSI). The accurate detection, comparation and classification of latch-up, upset, and functional interrupt were achieved. In host PC part, two customized software systems were developed, including the Procise for maximal resources occupation and a C^# based visual control interface for real-time communication. For hardware, a motherboard -daughterboard system guaranteed testing performance and kept its compatibility throughout testing. The fault injection and ¹⁸¹Ta³¹⁺ irradiation results indicated the validity of proposed measurements and the stability of hardware operation. Importantly, the high anti-irradiation performance of device was also verified.