IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543

この記事には本公開記事があります。本公開記事を参照してください。
引用する場合も本公開記事を引用してください。

Cache memory organization for processing in memory
Young-Kyu KimByungin MoonDong-Sun KimYoung-Jong Jang
著者情報
ジャーナル フリー 早期公開

論文ID: 16.20190393

この記事には本公開記事があります。
詳細
抄録

A promising solution for assuring ultra-low latency in data-intensive application processing systems is processing in memory (PIM). Although most studies that have examined PIM-based computing systems have used cache memory, few have adequately explored a reasonable cache management policy for PIM. Therefore, this paper studies cache management policies for PIM-based computing systems and classifies existing PIM policies according to where they are located and how they are managed. To evaluate the policies, we model three types of PIM-based computing systems used in an in-memory system architecture. One model employs an internal-single cache, another an external cache hierarchy, and the other internal multiple cache-based PIM. We also simulate the performance and power consumption of the three models by their workloads, each with diverse characteristics. The experimental results show how cache policies influence the performance and power of PIM-based in-memory computing systems.

著者関連情報
© 2019 by The Institute of Electronics, Information and Communication Engineers
feedback
Top