Article ID: 16.20190546
This paper demonstrates the design flow of a quick-start pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. The quick-start PWPLL converts the internal state into an analog-digital mixed signal called soft-thermometer-code (STC) and stores them into memory before PWPLL is turned off in order to enhance the start-up in the next turn-on. Our chip fabricated with TSMC 65nm shows 220ns settling time (13 reference clock cycles), 858μW power consumption under 1V nominal supply voltage with 59μm × 58μm silicon area. The measurement results demonstrate that the design-automated PLL realizes the FoM of −221.7dB, which is roughly the same value as that of the manually-designed one with the same target specification.
