論文ID: 16.20190600
This paper presents a novel bit-serial semi-systolic array structure to simultaneously execute modular multiplication and squaring operations in GF(2m). The architecture is explored by using a systematic methodology based on the proper choice of the scheduling and projection vectors applied to the algorithm dependency graph. The explored architecture has the advantage of sharing the data-path between the two operations, and hence it leads to saving more space compared to the case of using a separate data-path for each operation. Also, the simultaneous calculation of both operations significantly decreases the execution time required to perform modular exponentiation operation, as it mainly depends on these two core operations. Complexity analysis indicates that the developed bit-serial semi-systolic array structure outperforms the latest exiting competitor bit-serial systolic and non-systolic structures in terms of area-time (AT) by at least 24%. This makes the proposed structure more appropriate for use in resource-constrained cryptographic processors.
