IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
FPGA Implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance
Wei GeShenxin HuJiquan HuangBo LiuMin Zhu
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JOURNALS FREE ACCESS Advance online publication

Article ID: 16.20190670

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Abstract

Utilizing the randomness caused by process variations in chip manufacturing, PUF can provide identification and verification by generating unique challenge-response pair. The output response of Arbiter PUF is due to path delay differences from different input challenge. However, due to the strong linear correlation between the response and challenge of the Arbiter PUF, the attacker can model the APUF through a machine learning algorithm. This paper proposes a challenge pre-processing structure arbiter PUF (CPP-APUF), which increases the unknowingness of the input challenge, and improves the APUF's ability to resist machine learning attacks. The 64-stage CPP-APUF is implemented based on FPGA, the machine learning algorithm is used to attack the CPP-APUF. The output response prediction accuracy is lower than 61.33%, which is effective against the modeling attack of machine learning. Finally, the challenge-response pair obtained from experimentally verifies the PUF characteristics.

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© 2019 by The Institute of Electronics, Information and Communication Engineers
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