Floating-bulk transistors: an alternative design technique for CMOS low-voltage analog circuits

Jesus E. Molinar; Marco A. Gurrola; Ivan R. Padilla; Juan J. Ocampo; Carlos A. Bonilla; Jose M. Amezcua

doi:10.1587/elex.17.20190748

この記事には本公開記事があります。本公開記事を参照してください。
引用する場合も本公開記事を引用してください。

Floating-bulk transistors: an alternative design technique for CMOS low-voltage analog circuits

Jesus E. Molinar, Marco A. Gurrola, Ivan R. Padilla, Juan J. Ocampo, Carlos A. Bonilla, Jose M. Amezcua

著者情報

キーワード: Bulk-driven, floating-gate, quasi floating-gate, CMOS, low-voltage amplifier

ジャーナルフリー早期公開

論文ID: 17.20190748

DOI https://doi.org/10.1587/elex.17.20190748

この記事には本公開記事があります。

The final version of this article is now available: Vol. 17 (2020), No. 3 pp. 20190748-20190748

詳細

抄録

This letter details a novel floating-bulk transistor technique for low-voltage design. The approach is derived from two previous well-known techniques: bulk-driven and quasi floating-gate. The floating-bulk technique uses an input capacitive coupling through a floating bulk of a PMOS allowing modulation of the drain current. A fabricated common-source amplifier was tested on CMOS 0.5μm technology and the feasibility of the proposal was demonstrated.

責任著者(Corresponding author)

J-STAGEへの登録はこちら（無料）