Article ID: 17.20200025
The tunnel field-effect transistor (TFET) is one of the promising transistors which is expected to replace some complementary metal-oxide semiconductor (CMOS) circuits. Here, we apply a SPICE simulation of a Si TFET using high-K gate insulator to a simple circuit of 32-kHz crystal oscillator and compare the power consumption of Si TFET with conventional CMOSs calculated from the predictive transistor model (PTM). We considered L=65-nm and L=90-nm devices based on a table model whose values are derived from technology computer aided design (TCAD) calculations. We show that the power consumptions of TFETs are about 22.3% ∼38.6% lower than those of CMOSs for L=65-nm devices, and we show the 13.6%∼36.1% lower power consumption of TFETs for L=90-nm devices.