A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration

抄録

In this paper, an 8-channel 16 bit 200 kS/s successive approximation register analog-to-digital converter (SAR ADC) realized in 130 nm SOI CMOS technology is presented. A capacitor-resistor hybrid digital-to-analog converter (DAC) is adopted in this design to avoid the bulky capacitor array. In addition, an on-chip self-calibration technique is proposed to calibrate the mismatch of the capacitors in the DAC. To simplify the calibration logic of the resistor DAC, an auxiliary capacitor is added in the capacitor DAC to replace the resistor DAC for calibration. Moreover, the added auxiliary capacitor can also be utilized to correct the errors caused by the incomplete settling of reference voltage during the conversion. The measured results show that signal-to-noise-and-distortion-ration (SNDR) and spurious-free-dynamic-range (SFDR) compared with it without calibration are improved from 76.51 dB to 85.82 dB and 80.84 dB to 95.14 dB, respectively. The proposed ADC occupies an active area of 0.966 mm² and consumes a total power of 3.1 mW.