The design of large image rejection and wideband CMOS active polyphase filter for BeiDou RF receiver

Abstract

In this letter, a new circuit structure for CMOS active polyphase filter is proposed and analyzed. In the proposed structure, the currents produced from two cascode stage with a capacitor and single cascode stage in a single-stage are used to realize high-pass and low-pass functions, respectively. Compared to other conventional active polyphase filters, the proposed polyphase filter uses a simpler structure to achieve strong image rejection at the higher frequency while obtaining lower power consumption and smaller chip area. In the 0.18-μm CMOS process, the proposed active polyphase filter occupies less than 0.36mm² of chip area. From the measurements, the four-stage active polyphase filter shows an image rejection ratio of more than 58.2dB at frequencies of 26MHz to 65MHz, a voltage gain of 5.8dB and an IIP3 of 1.5dBm at 45 MHz while consuming only 2.64mA from a 1.8-V supply.