A 8 bits, 6.2 ps Resolution Two-Step Time-to-Digital Converter with Set-Reset-based arbiters and signal tracking mechanism

抄録

A low power, fine resolution and good linearity time-to-digital converter (TDC) for All digital phase-locked loops is presented. The proposed two-step TDC consists of coarse-TDC (CTDC), Coarse-Fine Interface and fine-TDC (FTDC). The CTDC adopts Set-Reset-based arbiters and signal tracking mechanism to reduce power consumption. FTDC employs Vernier delay-line to obtain fine resolution. The linear delay-line structure of CTDC and FTDC and Coarse-Fine Interface’s dynamic logic gate both contribute to good linearity. Implemented in 180 nm CMOS process，the TDC achieves 6.2 ps resolution and 8 bits range. It consumes only 520 µW and achieves the best figure-of-merit (FoM) compared with other state-of-the-art TDCs.