A 25-Gb/s High-Sensitivity Transimpedance Amplifier with Bandwidth Enhancement

Abstract

A 25-Gb/s transimpedance amplifier (TIA) is proposed and realised in a 0.18-μm SiGe BiCMOS process. A series-peaking network and a shunt-peaking network are used to increase the bandwidth of the modified TIA. A gain boosting circuit is used to optimize the input-referred noise. The chip occupies an area of 0.8mm², and consumes 82mW from a 3.3-V supply. The TIA transimpedance gain is ∼ 4.5K ohms. Bite error rate tests indicate that the sensitivity of the fabricated TIA is −13 dBm for a date rate of 25.78125-Gb/s (Bit error rate (BER) = 10⁻¹² ,λ=1310nm, ER=4.2dB, and 0.8 A/W PD responsivity).