Article ID: 17.20200371
A monolithic 12-bit digitally calibrated digital-to-analog converter (DAC) has been developed. The principle of proportional match design in the resistor switch network, its structural characteristics and the resistor network for calibration are presented. A close-loop calibration circuit with differential difference amplifier (DDA) has been proposed to eliminate the variation of switch resistance caused by temperature and supply-voltage. Moreover, this paper also presents the proposed automatic calibration algorithm based on fuse trim, which can reduce the number of times to trim the resistors and simplify the trimming process. The proposed self-calibrated and digitally trimmed DAC has been fabricated with a 0.5 μm bipolar-CMOS-DMOS (BCDMOS) process. Measurement results show that the integral nonlinearity (INL) and differential nonlinearity (DNL) of the developed DAC after calibration achieve -0.65 LSB∼+0.6 LSB and -0.6 LSB∼+0.25 LSB, respectively. The settling time of the developed DAC achieves 1 μs.
