A Full Matrix Joint Optimization Method for Hardware Implementation of AES MixColumns/InvMixColumns

Abstract

Among Advanced Encryption Standard (AES) operations, MixColumns/InvMixColumns is the second most computationally complex operation after S-box. It occupies a large hardware resources and critical path delay (CPD) in AES hardware implementations. To reduce the hardware complexity of the MixColumns/InvMixColumns, a whole matrix joint optimization method is proposed in this paper. All coefficient multiplications in MixColumns/InvMixColumns are combined into a single matrix multiplication in the proposed method, and larger number of common subexpressions can be shared in the combined matrix. Therefore, the area can be drastically reduced in implementations. The validity of our whole matrix joint optimization is verified by theoretical analyses and synthesis tools. Both analyses results and synthesized results indicate that, compared with column joint optimization and row joint optimization, the optimization efficiency is improved greatly in the whole matrix joint optimization. Compared with previous works, our implementations have wider area-delay tradeoff, from less delay to minimal area cost.