Memory test and repair technique for SoC based devices

抄録

System on Chip (SoC) architecture mainly consists of the memories in a larger area. Due to the availability of memories in a larger-size, it is difficult to test these memories for faults. Therefore, a smooth test solution to test these memories against fault and repair the faulty cells has introduced. In this research, we proposed a Memory Test Controller (MTC) to test the memories and Built-in Self-repair (BISR) mechanism to repair the faulty cells for any recent SoC based devices. The MTC not only identifies the fault, but it finds the type of fault available, and BISR block repairs the detected faulty cells. The paper provides empirical insights about how change is brought in features of the SoC based device after integrating both the proposed controller block. It is noticed that from the obtained results, the proposed methods are stands better in terms of the area overhead, power and timing when compared with the existing approaches.