A 92 fs_rms jitter frequency synthesizer based on a multicore Class-C voltage-controlled oscillator with digital automatic amplitude control

Abstract

This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm². By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.