Area and Energy-Efficient Buffer Designs for NoC based on Domain-Wall Memory

抄録

Networks-on-chip (NoC) is a major contributor to the power consumption in modern many-core processors, especially the router comprising large number of virtual channel (VC) first-in-first-out (FIFO) buffers. In this paper, we propose three buffer designs that leverage the unique serial access mechanism, non-volatility and high density of Domain-Wall Memory (DWM) to replace conventional SRAM based buffers in NoC router. Experiments demonstrates that the proposed DWM designs can achieve considerable improvement in area and power efficiency. The best performing proposed approach shows 36.1% (24.2%) area and 55.1% (24.5%) power saving over conventional SRAM (STT-MRAM) based designs respectively without performance degradation.