A Bit-Interleaving 12T Bitcell with Built-In Write-Assist for Sub-Threshold SRAM

Abstract

This paper presents a half-selected robust 12T bitcell with built-in write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column half-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.