Article ID: 19.20220267
A high-speed gate driver circuit which can meet both GaN FET and SiC MOSFET is presented. High-speed output drive circuit with wide output drive voltage is introduced in the driver circuit to improve speed and efficiency. By using high-speed level shift circuit and floating step-down low dropout regulator (LDO) circuit, the signal amplitude of the internal circuit for the output drive circuit is reduced, and the speed is greatly improved. Based on the proposed output drive circuit, a galvanically isolated 20 MHz 4 A gate driver using capacitive coupling with 5.5 V to 24 V output drive voltage is design and implemented in 180 nm BCD process. Test results show the prototype gate driver achieves the rise and fall time of 2.2 ns and 2.5 ns respectively under 5.5 V supply for GaN FET driving, and the rise and fall time of 4.1 ns and 4.6 ns respectively under 24 V supply for SiC MOSFET driving with 20 MHz frequency.
