A 1.9-ps 8× Phase Interpolation TDC for Time-based Analog-to-Digital Converter with Capacitance Compensation Self-Calibration

Abstract

This paper presents a 1.9-ps 8× phase interpolation time-to-digital converter (PI-TDC). This architecture enhances the resolution and conversion speed in cooperation with phase interpolation, high-frequency readout, and reset techniques. The prototype PI-TDC is designed in a 65-nm CMOS process with a 1-V power supply, achieving a 1.9-ps resolution at 2.5-GS/s. The simulated DNL is 0.85-LSB, and INL is 0.64-LSB. This PI-TDC is applied to a high-speed time-based analog-to-digital converter (TB-ADC) with a high-performance voltage-to-time converter (VTC) and the capacitance compensation self-calibration (CCS-CAL). The high-speed TB-ADC achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting a Walden FoM of 52.1-fJ/conv.-step.