論文ID: 20.20230008
A high voltage, external capacitor-less low-dropout regulator (HVLDO) with transient enhancement loop is presented in this work. The proposed HVLDO is designed with high withstand voltage laterally-diffused MOS (LDMOS) transistors and a transient enhancement loop is proposed to properly inject/sink current to/from the gate and output nodes of the power transistors to achieve fast transient response and high stability. Fabricated in 0.5 μm SOI BCD process, the HVLDO occupies an active area of 0.29 mm2. Operating with an input voltage ranging from 5.2 to 20 V, it supplies an output voltage of 5 V and a maximum load of 100 mA. For all load conditions, this design has the power supply rejection of -49 dB@ 100 kHz, the phase margin over 68.4 deg and achieves a temperature coefficient of 13.15 ppm/°C. Measurement results show that this design has a line regulation of 0.88 mV/V and a load regulation of 0.22 mV/mA. The proposed HVLDO features fast line transient response of 60/20 mV@ 9.8 V/µs, fast load transient response of 30/70 mV@100 mA/µs, and recovery time of 2 µs without external capacitors. Compared with the prior art, this work achieves the best transient FOM of 12.19 fs.
