IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Enhanced Darlington fT-doubler Structure in a 25 GS/s Track-and-Hold Amplifier for Bandwidth Improvement
Luning XiaoWenxiang ZhenYongbo SuZhi Jin
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JOURNAL FREE ACCESS Advance online publication

Article ID: 20.20230191

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Abstract

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( fT). Broadband operation is achieved using an enhanced degenerated Darlington fT-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional fT-doubler structures, the enhanced cascode Darlington fT-doubler structure reduces the “VCE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher VCE for amplifying transistors, which represents higher fT,peak performance. Benefiting from the proposed Darlington fT-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- fT bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

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© 2023 by The Institute of Electronics, Information and Communication Engineers
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