An Enhanced Reconfigurable Dual-Clock FIFO for Inter-IP Data Transmission

抄録

In integrated designs of multiple IP cores across clock domains, signal metastability can occur due to unequal wiring and variations in PVT. This leads to inconsistency between the signals obtained by the target and the signals at the source. Establishing a FIFO is one of the crucial methods for addressing data inconsistency. Therefore, this paper proposes a novel array structure based on one-hot coding, where the row and column codes generated by Johnson counters are XORed to create the address pointer. This innovation reduces the area for the FIFO and enables rapid control logic using one-hot coding. Furthermore, a state-based approach is employed to mitigate the impact of memory size on the empty/full detection circuit. It only records the read-and-write addresses, enhancing the reconfigurability of the FIFO. Using the SMIC 0.18µm process, the synthesis and simulation results demonstrate that the FIFO can achieve a maximum operating frequency of 830MHz. Additionally, compared to similar synchronous FIFO, it exhibits a significant 30% reduction in area. When considering different FIFO depths and widths, the method proposed in the paper shows an area reduction of 30% to 47% compared to similar synchronous methods. For a depth of 16 and a data width of one word, the power consumption is about 6.8 mW. The FIFO presented in this paper can serve as a reference for data transmission between different clock domains.