A 12-bit 2.32 GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer

抄録

This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175 mW.