PN-APUF: A MOSFET threshold loss based strong arbiter PUF with double-edge sampling

Abstract

Arbiter physically unclonable function (APUF) is one of the most representative strong PUFs. Improving traditional APUF can enhance the performance of APUF-based PUFs. Accordingly, based on the theoretical foundation of traditional APUF, this paper proposes a novel PUF that utilizes the threshold loss, in which the PMOS transmits at a low level and the NMOS transmits at a high level, as the deviation source. In this manner, we significantly extended the delay deviation of both the rising and falling edges, thereby improving the randomness of PUF. The proposed PUF passed six subtests of the NIST randomness test suite. The delay unit only uses 20 minimum-size transistors with a fully custom layout area of 6.14 μm² in the TSMC 65-nm process, reducing the area by 15% compared to traditional APUF. The core area feature size is 93,018 F² which is more than sixfold reduction to the voltage-based PUFs. Furthermore, the proposed PUF generates twice the number of challenge-response pairs by sampling the rising and falling edges. It also exhibits a superior resistance against machine learning attacks compared to APUF, making it a better alternative.