A 10-bit 40 MS/s SAR ADC With a Low-Noise Low-Offset Dynamic Comparator and a High-Linearity Sampling Switch

Abstract

This paper presents a 10-bit 40 MS/s successive-approximation-register analog-to-digital converter (SAR ADC). To enhance the performance of the ADC, a high-linearity CMOS complementary bootstrap sampling switch (B-CMOS-SW) and a low-offset, low-noise double-tail dynamic comparator (LOLN-DT) are proposed. The ADC with the proposed comparator and the bootstrap switch is fabricated in a 40-nm 1P6M CMOS technology. Simulation results show that the proposed comparator achieves a low offset voltage of 3.4 mV at 1 σ, which reduces half compared with conventional Double tail (DT) dynamic comparator, and the input reference noise is 0.3 mV at 1 σ. Also, the proposed bootstrap switch improves the sampling nonlinearity above 6 dB. At 1.2V supply and 40 MS/s, the ADC reaches a SINAD of 57 dB, the SFDR reaches more than 70 dB, and the power consumption is 0.2 mW, leading to a figure-of-merit (FOM) of 9.76 fJ/conversion-step.