A Multimode SHA-3 Accelerator based on RISC-V system

抄録

Nowadays, almost all fields cannot lack security, from the essential encryption/decryption to hash function algorithms. The Secure Hash Algorithm 3 (SHA-3) with four modes, SHA3-224/256/384/512, is a known new hash function due to being more secure than its predecessors, SHA-1 and SHA-2. While hardware implementations of SHA-3 have been extensively studied, the primary focus has often been on optimizing the KECCAK algorithm. This paper introduces an efficient multimode SHA-3 architecture (MS3) featuring configurable buffers and a sub-pipeline KECCAK design. These innovations aim to save resources and boost throughput, respectively. Furthermore, MS3 is integrated with the reduced instruction set computer five (RISC-V) system as a hardware accelerator via the TileLink bus. This integration enables MS3 to communicate with RISC-V for configuration purposes and utilize direct memory access (DMA) for efficient data transfer with memory. Experimental results on the Cyclone IV E platform demonstrate MS3 achieving approximately 500 Mbps throughput across all modes, with DMA achieving a throughput of 540.21 Mbps. Additionally, our design exhibits superior efficiency compared to existing works on Virtex 5, 6, and 7 FPGA platforms. Specifically, MS3 achieves throughputs of 11.07 Gbps, 14.52 Gbps, and 17.29 Gbps, with corresponding efficiencies of 10.31 Mbps/Slice, 15.03 Mbps/Slice, and 18.39 Mbps/Slice, respectively.