論文ID: 21.20240164
This article presents a second-order cascaded integrator feedforward (CIFF) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) reusing a dynamic amplifier. The proposed NS architecture uses a gain-optional floating inverter amplifier (FIA) and a sampling-before-integration technique to realize sharp noise transfer function (NTF) with minor extra capacitance. Implemented in 180-nm CMOS technology, the proposed NS-SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 88.6 dB over a sampling frequency of 1.6 MHz and an oversampling rate (OSR) of 16 while consuming only 250 µW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 171.6 dB, proving the proposed ADC fulfils considerable performance with both high resolution and low power consumption.
