Article ID: 21.20240199
A novel capacitor-less low-dropout regulator (CL-LDO) is presented that achieves transient and stability enhancements through the addition of an active capacitor and a dynamically biased buffer. To enhance the transient response, an active capacitor is proposed, resulting in a significant reduction in overshoot, undershoot, and settling time. Furthermore, the dynamically-biased buffer, comprised of a super-gm source follower, effectively enhances the loop stability. Implemented and fabricated in 0.18 μm SOI BCD technology, the CL-LDO generates a stable output voltage of 1.8 V in the input voltage range from 2.8 V to 3.8 V, with a maximum load current of 100 mA and a quiescent current of 94 µA. When the load current steps from 0 mA to 100 mA, the measured results of overshoot and undershoot are 240 mV and 110 mV, respectively. The proposed CL-LDO has superior line regulation of 0.94 mV/V and load regulation of 12.66 mV/A.
