Multi-transition Delay Test for Improving the Coverage of Cell Internal Defects

抄録

Weak resistive defects in standard cells exhibit subtle electrical behaviour that may lead to test escapes, thereby compromising the reliability of integrated circuits. Fault analysis data has shown that the presence of weak defects in specific cells can cause variations in output timing when multiple transitions occur on the inputs, as opposed to a single transition. However, existing delay test generation tools do not account for the effect of multiple input switching (MIS). In this paper, the effects of MIS on defect detection and timing analysis are analyzed and a multi-transition delay test method is proposed to further expose and detect cell internal defects. In addition to sensitizing the selected paths, the new test pattern attempts to maximize the off-path input transitions, thus increasing the propagation delay of the selected paths or the proportion of incremental delay introduced by the defects. The simulation results on ISCAS benchmark circuits show that the proposed method achieves a maximum of 8.73% and an average of 5.99% defect coverage gain compared to the existing delay tests that based on single input switching schemes.