論文ID: 21.20240500
This paper presents a fully synthesizable spread spectrum clock generator (SSCG) based on a fractional-N Digital PLL (DPLL). The designed SSCG adds a triangular digital signal to the frequency control word (FCW) to down-spread the frequency of the clock signal and reduce its electromagnetic interference (EMI) to near signals. Because of the linear frequency modulation of the triangular signal, the designed DPLL can be configured to operate in a Type-III mode to track the frequency variation more accurately than a Type-II setting. A proof-of-concept prototype was built using a 65 nm CMOS technology. The measured EMI reduction because of the SSCG operation was 22.0 dB. The designed SSCG is based on a fractional-N DPLL, which gives a 1.0 GHz signal from a 100 MHz reference frequency and consumes 4.83 mW and 3.1 mW from a 1.2 V DC supply in the fractional and integer mode of operation, respectively. The measured rms jitter of the designed prototype was 3.95 ps and 2.1 ps in the fractional and integer modes of operation, respectively. The core area of the developed prototype is 0.1 mm2.
