Article ID: 21.20240587
Approximate computing is a promising approach to reduce power consumption in error-resilient applications with lax precision constraints. This paper presents an energy-efficient approximate multiplier with a novel imprecise 4-2 compressor based on incomplete-sorted circuits. The proposed approximate multiplier includes three parts: a most significant bit (MSB) compressed circuit, a middle-bit accumulation circuit, and a least significant bit (LSB) truncation circuit. First, we propose an ultra-low power approximate 4-2 compressor to improve efficiency, which is used for the middle-bit accumulation circuit. Then, since the weight and input distributions in neural networks usually follow a normal distribution, the MSB compressed circuit performs approximate computation on the accumulation of the significant bits. Finally, constant compensation in the LSB truncation circuits is utilized to balance accuracy and efficiency. Experimental results show that the 8-bit proposed design significantly improves the power-delay product (PDP) by 71.49% with satisfactory performance when compared with the traditional Dadda multiplier.
