A switch-reduced data weight averaging technique for multi-bit Sigma-Delta modulator

抄録

Due to its simplicity in circuit implementation, conventional Data Weighted Averaging (DWA) is commonly used to calibrate capacitor mismatch in feedback DACs. However, for low-amplitude input signal, the non-random use of capacitor elements causes periodic mismatch errors, leading to harmonic distortion in the signal band. Consequently, this results in significant harmonic distortion within the signal band. This paper proposes a randomized DWA algorithm that utilizes the amplitude of the input signal to control the starting position of DAC elements for each cycle, thereby suppressing tones caused by DAC element mismatches. Compared to the conventional DWA algorithm, this approach achieves higher linearity while reducing DAC switching activities. To evaluate the proposed algorithm, a second-order discrete-time sigma-delta modulator model was designed. Simulation results indicate that the proposed algorithm achieves up to a 14% reduction in switching activities and extending the dynamic range by approximately 5 dB compared to the conventional randomized DWA algorithm.