Article ID: 22.20240731
This paper presents a design method aimed at enhancing the high-efficiency fallback range of ultra-high-power Doherty power amplifiers. This method integrates 27mm and 36mm gate-width chips into a dual channel device by optimizing the internal matching design. It employs an asymmetric design combining a power input ratio of 1:2 and a power ratio of 2:3 to extend the fallback range and minimize efficiency degradation. Additionally, an enhanced Π-type double impedance matching and fifth- stage post-matching design were proposed to address the limitations of narrowband performance. Finally, a 470W asymmetric Doherty power amplifier based on GaN HEMT was developed. The measured results indicate that within the 2.50-2.75 GHz frequency range, the amplifier achieves a saturated output power of 56.3-56.7 dBm, a linear region gain of 17.2-17.9 dB, and a saturated drain efficiency of 68%-73%. At an 8 dB power back-off, the drain efficiency ranges from 59% to 64%. This method presents an effective scheme for achieving a high-efficiency fallback range in ultra-high-power Doherty amplifiers.
