Ultra-Low Power and 1.5 Bit/Cell Ternary-SRAM Stability Modeling for Always-on Applications

Abstract

We present an ultra-low power ternary SRAM (T-SRAM) with a storage capacity of 1.5 bit/cell, using a commercial 110-nm CMOS foundry for always-on applications, along with an analysis of its stability. By designing T-CMOS with SPICE compact model parameters, which are body-effect coefficient (m), peak electric field coefficient (C_EP), and gate width (W), band-to band tunneling current (I_BTBT) can be reduced to hundreds of fA range and it allows V_DD to scale down to 0.55 V. Finally, we experimentally demonstrate T-SRAM cell which static and dynamic powers are decreased to 4.5x10^-2 and 1.3x10^-7, respectively.