Article ID: 22.20250047
Mismatched circuit components in analog-to-digital converters (ADCs) caused by imperfect fabrication processes significantly degrade the ADC performance, and there have been various attempts to address this by carrying out on-chip ADC calibration. However, calibration accuracy suffers from the defects of on-chip circuitry (called design-for-calibration (DfC) circuits) designed to facilitate those calibration processes, which are introduced by variations in the manufacturing process.
Unfortunately, it is hard to calibrate on-chip DfC circuit itself on a device-by-device basis, because of low controllability and observability for on-chip circuits. This paper proposes an efficient built-off self-calibration methodology to externally calibrate ADCs on the proposed load board, by making a detour around the nonlinear portion of a code-width (CW) based on the differential-nonlinearity (DNL), thereby improving ADC linearity. This work migrates the required DfC circuitry to an external load board as well as bare dies wherever possible, in order to eliminate even the possibility of the degradation by on-chip DfC circuits. For simplicity, it is assumed that the mid-code of an ADC has a CW that is wider than a least-significant-bit (LSB) voltage, i.e., wide CW to be calibrated only. The key idea of this work is as follows: the transfer function (TF) for the ADC can be split into two halves, i.e., an upper TF and a lower TF to calibrate the mid-code. If an input signal falls in the upper TF, then it is shifted up by half of the remaining width at the mid-code, excluding one LSB voltage. Similarly, if an input signal falls in the lower TF, then it is shifted down by half of the remaining width. As a result, any input signal can bypass the remaining width at the mid-code, excluding one LSB voltage, so that the TF can be linearized. This process can be realized using the proposed load board configured with an analog adder, a comparator, a binary-weighted capacitor array called level shifter, and a simple digital logic called level logic including a computation logic and a switch logic. To evaluate the performance of the proposed work, a 12-b 40-MSPS split-capacitive digital-to-analog converter successive-approximation ADC under calibration and the proposed circuitry with 8-bit capacitor array were separately designed in 0.18-µm CMOS. Simulations based on this work verified that the proposed methodology can be practically used, by showing that the total-harmonic-distortion was enhanced from 71-dB to 81-dB.
