A 6 bits 10 MS/s SAR ADC with Multi-Conversion Dynamic Amplifier

抄録

This paper presents a 6 bits 10 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing a multi-conversion dynamic amplifier (MC-DA) to enhance power efficiency. The MC-DA enables voltage-time conversion on both rising and falling clock edges, reducing clock frequency and dynamic power consumption. A shoot-through prevention (STP) latch ensures accurate conversions, while a reset generator accelerates reset times, improving throughput. A dual-ring counter-based clock generator optimizes phase alignment. Measurement results from a 0.5 μm CMOS implementation show a signal-to-noise and distortion ratio (SNDR) of 34.52 dB and a spurious-free dynamic range (SFDR) of 43.08 dB. The proposed ADC achieves significant power savings, making it suitable for low-power applications.