論文ID: 22.20250220
This paper presents a high-speed single channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) for ultra-high-speed system. The ADC operates in two modes: 1GS/s 8-bit and 1.5GS/s 6-bit. A floating-skip algorithm is proposed to address the speed limitation and amplitude attenuation of input signals in 6-bit operating mode, while avoiding unnecessary switching power consumption. Meanwhile, the ADC employs binary redundant CDAC to improves the fault tolerance range and relaxes the requirements for setting accuracy, further achieving high conversion speed. The reconfigurable ADC is designed in the 28-nm CMOS process, it achieves the 36.69-/47.68-dB signal-to-noise-and-distortion ratio (SNDR) at 1-/1.5-GHz sampling rate with the same power consumption of 4.42 mW. The ADC core occupies an active area of only 0.003948 mm2. It achieves a FoMw of 22.31 fJ/conv.-step at 8-bit conversion mode.
