論文ID: 22.20250244
This paper proposes a background digital calibration technique for high-speed multi-channel time-interleaved ADCs (TI-ADCs) to address sub-channel memory nonlinearities and inter-channel mismatch errors. The method employs a simplified DDR-based Volterra series model with reduced parameters. An improved Input-Free Band (IFB) error detection scheme eliminates the need for reference channels or test signals, ensuring uninterrupted ADC operation. To effectively overcome non-convex optimization challenges, the proposed approach employs a customized artificial bee colony (ABC) algorithm to extract Volterra kernel coefficients. Validated through simulations and a 1-Gsps 14-bit 2-channel PI-SAR ADC prototype, the technique demonstrates effective compensation for subchannel memory nonlinearities and inter-channel first-order mismatches, achieving SFDR improvements of 11.67-24.69 dB across input frequencies. The fully-digital solution offers versatility and portability for diverse ADC architectures.
