Article ID: 22.20250300
The inherent open instruction set architecture of RISC-V processors, while promoting flexibility and customization, also renders them susceptible to Hardware Trojan (HT) attacks. Addressing this critical vulnerability is paramount for ensuring the security and integrity of modern computing systems. In this work, we present a novel real-time HT detection methodology for RISC-V processors by monitoring data and address path changes tied to core instructions and strategically leveraging pipeline node characteristics. It eliminates the need for a Golden Chip reference or extensive gate-level features. Upon detection, in-pipeline recovery is triggered. Validation on a three-stage RISC-V processor demonstrates that all tested HTs are reliably identified, with processor recovery completed within three clock cycles. Hardware implementations on FPGA and 40 nm CMOS technology substantiate rapid recovery and robust security protection.
