High-Speed Double-Error-Correction Coding Scheme for NOR Flash Memories

Abstract

Double-error-correction (DEC) BCH codes, a class of binary cyclic codes, have been widely used for error correction in NOR flash memories. However, the decoding process of these codes involves the complicated cubic operations in binary extension fields. In order to address the problem, this paper proposes a DEC coding scheme for NOR flash memories based on Melas codes. A high-speed decoder with the step-by-step decoding algorithm for these codes is proposed and an associated parallel architecture is designed to meet the low latency requirement. It is worth mentioning that the cubic operations in binary extension fields can be avoided, which can reduce the latency of the error pattern calculation. For verification, the designed decoder architecture is applied to a (274, 256) shorten Melas code as an example, which can achieve a throughput rate of 3.6 Gb/s with a clock period of 2 ns.