An SRAM-based chunked computing-in-memory macro with a multi-slope voltage-time-digital converting ADC for efficient MAC operations

抄録

To address power-sensitive neural network applications at the edge, computing-in-memory (CIM) with reduced data transfer costs has been proposed. The power and area overhead of traditional ADCs limits the efficiency of analog-based CIM. This paper proposes a CIM macro with a novel data-sensitive multi-slope (DSMS) voltage-time-digital converting (VTDC) ADC to efficiently perform multiply-and-accumulate (MAC) operations. The VTDC measures the bit line recharging time to reduce the need for high-cost ADCs. The DSMS technique adjusts the voltage-time slope based on input data to further optimize energy consumption and conversion time. The chunked array control (CAC) circuits facilitate faster weight updates. The CIM macro achieves an energy efficiency of 631 TOPS/W and an area efficiency of 8.4 TOPS/mm² for binary MAC operations. It exhibits less than 1.5% accuracy loss on the MNIST and CIFAR-10 datasets compared to the software baseline.