AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

抄録

The Advanced Encryption Standard (AES) is a fundamental cryptographic algorithm widely used to secure data in embedded systems, IoT devices, and cloud computing platforms. However, recent research on AES hardware accelerators face challenges in achieving high performance and hardware efficiency, particularly when supporting multiple modes and key sizes. To address these limitations, this paper proposes a hardware-efficient RISC-V accelerator with low-latency AES instruction extension (AES-RV), designed to enhance both processing speed and energy efficiency across various AES configurations. Specifically, AES-RV incorporates three key optimizations: high-bandwidth internal buffers for continuous data processing, a specialized AES unit with low-latency custom instructions, and system pipelining with a ping-pong memory transfer mechanism. The AES-RV accelerator is implemented and evaluated on a real-time Xilinx ZCU102 FPGA system-on-chip (SoC), utilizing 29,608 FFs, 32,483 LUTs, and 12 BRAMs. Performance comparisons against a baseline RISC-V implementation for multiple AES modes and key sizes demonstrate latency improvements ranging from 195.5 times to 255.97 times. Additionally, evaluations against powerful CPUs and GPUs in real-time AES executions reveal energy efficiency gains of 9.92 times to 453.04 times. Compared to state-of-the-art AES hardware accelerators, AES-RV achieves throughput improvements of 13.56 times to 33.52 times, energy efficiency enhancements of 2.36 times to 58.76 times, and area efficiency gains of 91.42 times to 638.8 times.