論文ID: 22.20250366
This paper presents an adjustable CMOS voltage reference that achieves a low temperature coefficient (TC) through a novel curvature-compensation technique. The design employs thin/thick-gate NMOS and PMOS pairs to generate complementary voltages (ΔVGS and ΔVSG) with opposing second-order curvature. Dynamically scaling ΔVGS via a programmable k-coefficient and summing with ΔVSG enables output adjustability and low TC. Implemented in 180 nm CMOS, post-layout simulations show 0.5-0.95 V output range with average TC of 5 ppm/°C (best) to 15 ppm/°C (worst) from -40°C to 125°C. The circuit consumes 456.5 nA at 27°C and achieves -51 dB PSRR (@100 Hz).