Low-Power non-redundant transition Sense Amplifier Based Flip-Flops With Conditional Pre-charge And Completion Detection

Abstract

In digital systems, optimising the power and delay of flip-flops (FFs) can remarkably enhance its performance. In this paper, an ultra-low power flip-flop (CPCDFF) based on sense amplifier is proposed. The conditional pre-charge (CP) circuit achieves non-redundant transition, which enables power wastage to be reduced. A lite-latch structure is proposed to effectively reduced the CK-to-Q delay of the FF. The proposed completion detection (CD) technique effectively improves the reliability of the FF at near-threshold voltage. The proposed FF is implemented in 22 nm process, and a comprehensive analysis. At 0.8V supply voltage, the post-layout simulation results show that the power of the proposed FF is only 0.151 µW@500MHz and 10% data toggle rate; the power delay product is only 1.473 nW*ns@20MHz at 20% data toggle rate. The Monte-Carlo simulation results considering the process, voltage, and temperature (PVT) variations indicated that the proposed FF could operate reliably down to a supply voltage of 0.4 V.