Article ID: 22.20250447
The single-transistor-clocked DET (STC-DET) effectively addresses the timing convergence issue in single-edge-triggered for high-frequency applications while reducing power consumption losses caused by redundant transitions. However, the introduction of the single-transistor-clocked buffer creates a more complex transistor stress distribution as well as a transmission network, and the low-power strategy based on a low supply voltage also makes the circuit more sensitive to threshold voltage degradation. This paper focuses on the STC-DET flip-flop as the research subject, employing transistor-level aging analysis to identify aging-sensitive transistors through de-aging analysis. A combination of transistor-level gate length tuning strategy and circuit structure optimization is applied for effective anti-aging design. Analysis results show that this optimization strategy significantly reduces the overall delay increase after aging under all corners. Notably, under the typical TT process corner, the 0→1 delay increase of the BOTTOM module is reduced by 58.2%, demonstrating the superiority of the proposed method.
