Successive approximation analog-to-digital converter based on capacitor weight self-calibration

Abstract

A 12-bit capacitor weight self-calibration successive approximation analog-to-digital converter (SAR ADC) is presented. The amplifier structure with Output-Offset Storage (OOS) technology is used to optimize circuitry to lower comparator offset voltage and noise. The bottom-plate sampling suppresses charge injection, thereby improving linearity and noise performance. The design also employs capacitive weight self-calibration with a proposed sign-aware two’s complement mapper, which enhances the ADC’s signal-to-noise-and-distortion ratio (SNDR) to 72.09 dB and demonstrates excellent conversion accuracy. The proposed ADCs were fabricated in a 0.18μm 1P6M CMOS process. It consumes 36.8 mW, occupies an active area of 1117μm×717μm using 1.8V supply and the sampling rate of 3 MS/s.