A Challenge Selection Approach for Delay-based Physical Unclonable Function on FPGA Utilizing Delay-Balancing Analysis: A Case Study on Arbiter PUF

Abstract

This paper presents a novel challenge selection methodology for delay-based physical unclonable functions (PUFs), which effectively balances the delay skew induced by asymmetric routing and enhances the uniformity of FPGA implementations. A mathematical delay model of PUF is established to analyze the asymmetry characteristics in FPGA architectures, including the routing discrepancies between delay elements and the non-equivalent signal paths within lookup table-based (LUT-based) delay elements. To mitigate the impact of non-ideal factors, a delay-balancing analysis approach is proposed to equalize the delays of asymmetric routing paths. A challenge selection algorithm is then developed to identify optimal symmetric paths based on the delay-balancing results. As proof of concept, six 64-bit arbiter PUFs (APUFs) are implemented to validate the proposed approach. Experimental results demonstrate that 25% of challenges are selected from a 16-bit challenge space, significantly improving the uniformity compared to the pre-selection approach.